VHDL is a hardware description language that can be used to model a digital system at many levels of abstraction. Its powerful features enable modeling designs with high degrees of complexity. This book aims at introducing the VHDL language to the readers in a user-friendly, readable style, concentrating only on the most useful aspects of this language. It is contemporary and uptodate as it incorporates the popular and widely used IEEE, STD_LOGIC_1164 package. It is a must-have book for any one who wants to leverage the remarkable power of VHDL, and will help one master key VHDL techniques such as Behavioral, dataflow and structural modeling Generics and configurations Subprograms and overloading Packages and libraries Model simulation Advanced features include: Entity statements, generate statements, aliases, guarded signals, attributes, and aggregate targets. The extensive hardware modeling coverage of the book includes modeling of regular structures, delays, conditional operations, state machines, Moore and Mealy FSMs, clock dividers, and much more.